module ysyx_22040213_branchif(
	input jumpb_en,
	input [2:0] funct3,
	input [63:0] data1,
	input [63:0] data2,
	output reg jumpb
);

wire signed [63:0] sdata1;
wire signed [63:0] sdata2;
assign sdata1 = data1;
assign sdata2 = data2;

always @(*)begin
  if(jumpb_en)begin
	jumpb =1'b0;
	case(funct3)
		3'b000 : jumpb = (data1 == data2)?1'b1:1'b0;
		3'b001 : jumpb = (data1 != data2)?1'b1:1'b0;
		3'b100 : jumpb  = (sdata1 < sdata2)? 1'b1:1'b0; //blt
		3'b101 : jumpb  = (sdata1 >= sdata2)? 1'b1:1'b0; //bge
		3'b110 : jumpb  = (data1 < sdata2)? 1'b1:1'b0; //bltu
		3'b111 : jumpb  = (data1 >= sdata2)? 1'b1:1'b0; //bgeu
		default: jumpb = 1'b0;
	endcase
  end
  else jumpb = 1'b0;
end


endmodule
